Front End Information - Design to Simulation

Silicon Design means design a system by adding Flops or Latches or Combo logic like AND, OR logic gates. These are the smallest unit of HDL language by which we make our system. These Flops or logic gates are made of transistors and they have different characteristics depends on library used but here we will discuss only design using flop and logic gates. So any logic equation equivalent logic design can be solve by K-Map, but when number of variable increases then it is difficult to manually add logics gates and design.

So to solve the problem we need upper level hardware descriptive language (HDL), which can make design coding easy and conversion from HDL language to RTL is done by synthesis tools. In Industry mainly two HDL language used.

1. Verilog
2. VHDL

Both language have similar way of coding or programming. Both have synthesizable as well as  non-synthesizable constructs. Design used for FPGA Prototyping should have synthesizable constructs only. Here the list of some frequently used verilog constructs.

1. Synthesizable Constructs - These constructs are used in designing of DUT (design under test) and TB (testbench).

S.No	Type	Name	Comments
1.	IO Ports	input, output, inout
2.	Module	module
3.	Parameters	parameter	passing the arguments in modules
4.	Functions	function and task	Combo logic only
5.	Data flow	assign	Wire and combo logic
6.	Loops	for, while, forever
7.	Procedural	always
8.	Conditional	if, else, case
9.	Define	‘Ifdef, ‘else, ‘end	Define statements.
10.	Operator	Arithmetic	+, -, *, /, %
11.	Operator	Logical	!, &&, ||
12.	Operator	Conditional	?
13.	Operator	Concatenation	{ }
14.	Operator	Bit wise operation	&, |, ^,~
15.	Operator	Relation	>,<,>=,<=,==,!=
16.	Operator	Shift	>>,<<

2. Non-Synthesizable Constructs - These constructs are used in designing of TB (testbench) only.

S.No	Type	Name	Comments
1.	Timed	time	Time & delay data type is not supported
2.	Real	real	Real data type is not supported
3.	Initial	initial	Mostly used in testbench
4,	Force /Release	force & release	Used in forcing signals in testbench
5.	Fork/Join	fork/join	Mostly used in testbench
6.	Deassign	Deassign	Rarely used

Verilog or VHDL language is similar to ‘C’ language even name and functionality of constructs are similar but while coding Good designer know the key difference between both languages that is ‘HDL’ is not sequential language like 'C' and what you will code in 'HDL' is finally going to convert in Combo and Flops. In ‘HDL’ we have output at each clock edge. So while designing with 'HDL' designer should also think hardware equivalent circuit of its design. This also help the back-end tools like synthesis and Place&Route tools to do their job.

Let’s see an example of 4 bit counter. Counter increment by one at each clock when ‘enable’ input is HIGH and reset to zero till input ‘enable’ is LOW.

1st we understand the requirements before writing the verilog code for above system. Above system have 2 inputs ‘enable’ and ‘clock’ and 4 outputs ‘b4c_out[3:0]’. ‘b4c_out[3]’ represents upper bit and ‘b4c_out[0]’ represents lower bit.

// 4 bit synchronous counter with enable

module bit4_counter (clock,enable,b4c_out);

input clock,enable;

output reg [3:0] b4c_out;

always @(posedge clock) begin

if(enable == 1’b1) begin

b4c_out <= b4c_out + 1’b1;

end

else

begin

b4c_out <= 4’b0;

end

end

endmodule

When design is complete we can take this design for back-end process but that will take some time and if the design will not work, it is difficult to exact  route cause the problem only reviewing RTL (HDL Code). So before jump to synthesis we can Simulate the design to check its functional behavior. To simulate the design or DUT we need to give stimulus to DUT through its interfaces.

Testbench + DUT

We can write TB or Testbench in verilog or in system-verilog. We are not going to synthesize it so we can use any constructs to build testbench. It has following components

• Interface with DUT
• Stimulus to DUT
• Checker and wavedump.

It is very important that stimulus is correct because against that stimulus only we are testing our design. Most of simulation tools give facility of dumping waveform which help in debugging the exact problem.

Testbench for 4 bit counter and waveform dump is

// testbench for 4 bit counter is

`timescale 1ns/1ps

module testbench;

reg ENABLE;

reg CLOCK;

wire [3:0] B4C_OUT;

bit4_counter bc4_cnt (

.clock   (CLOCK),

.enable  (ENABLE),

.b4c_out (B4C_OUT));

initial

begin

CLOCK = 1’b0;

forever #10 CLOCK = ~CLOCK;

end

initial

begin

ENABLE = 1’b0;

#100 ENABLE = 1’b1;

end

initial

begin

#5000 $finish;

end

// dump waveform

initial

begin

$dumpfile(“B4C_CNT.dsn”);

$dumpvars(4,testbench);

end

endmodule

Waveform dump (viewed in Cadence Simvision waveform viewer)