Back End Information - Synthesis to Bit file Generation

Back end flow for FPGA Prototyping mainly contain two process after that we can generate BIT file or Binary File for programming the FPGA. Those two process are -

1.     Synthesis.

2.     Place & Route.

Let’s see FPGA Synthesis first.

• So what is FPGA synthesis and is it different from ASIC synthesis ?

Similar to ASIC synthesis, FPGA Synthesis also convert RTL to optimized gate level netlist. Generally synthesis tools do following steps for synthesis

1.     Compile – Syntax check, HDL code optimization.

2.     Map – Library and Technology mapping.

We can understand synthesis by following simple example.

Let we have following HDL code (in verilog) -

assign net_x = input_a & input_b ;

assign net_y = input_b & input_c ;

assign output = net_x | net_y ;

After Compile tool perform following optimization -  

output_1 =  input_b  OR  input_c;

output = output_1  AND  input_b;

After Map we get following synthesis output -

OR_2 (o.(output_1), i1.(input_a), i2(input_c))

AND_2 (o.(output), i1.(output_1),i2(input_b))

FPGA Synthesis tools gives output in different file formats like “.v”, “.edn” and “.edif” ect. P&R tools mostly use “.edif” format for bit file generation. Acronym for for EDIF is ELECTRONIC DATA INTERCHANGE FORMAT.

Now let’s discuss that is there any difference between ASIC synthesis and FPGA synthesis ?

There are many difference between these two synthesis. FPGA synthesis is much more simple than ASIC synthesis. Let’s discuss in little detail so that we can better understand it.

1. For synthesis both have different target libraries.
2. ASIC libraries are  technology dependent.
3. Scan insertion, Memory BIST and DFT are not required for FPGA synthesis, because FPGAs are pre-manufactured and tested  hardware.
4. Clock tree synthesis is not required for FPGA, pre-build clock tree structure is already there.
5. Memory used in FPGA is different from ASIC. Generally all FPGA have limited size dual port memory.
6. Constraint file (SDC file) is much more simple for FPGA than ASIC synthesis.
7. Different tools used for FPGA and ASIC synthesis. Some examples are

FPGA synthesis - Synplify Pro and Premier (Synopsis), Precision (Mentor Graphics) etc.

ASIC synthesis - DC (Synopsis) and RC (Cadence) etc.

Ones synthesis completed and we analyze the synthesis report, we do Place & Route (P&R). P&R tool take synthesized design and a constraint file as input. This constraint file called ‘User Constraint File (UCF)’ or Design Constraint File. We need to write following information in this file.

1. Pin muxing information - if design has signals coming out from FPGA or going into FPGA then we need to assign corresponding FPGA pins for communication. For example UART, JTAG, RESET, any external clocks etc.
2. Write information of primary and derived clocks of design.
3. If two clock source are asynchronous in nature then assign them false_path.
4. If any path take more than one clock cycle then assign them as multi_cycle_path.

There are few more arguments available for write constraint file. That we can write as per our design requirements. If we not give constraint to the tool then it take random values for pin muxing. Generally P&R tools take following steps.

1. Constraint Placement - Place the blocks depends on constraints.
2. Global Placement - Place the rest unconstrained blocks.
3. Routing - Route the signals depends on block placements.

The output of the P&R tool are the ‘bit file’ and ‘post timing report’. After analysis of timing report we can use that bit file in our FPGA for Prototyping.

Some commonly used tools for FPGA Prototyping in the market are ISE and VIVADO by Xilinx, Libero by Microsemi etc.

We will discuss ‘Synthesis Design Constraint (SDC)’ and ‘Synthesis Result Report (SRR)’ in more detail in my next post soon.

Also discuss effect of Constraint File on Timing Report.