VLSI Design Overview and Questionnaires

This blog provides an overview of various practical concepts related to Synthesis, STA, Low Power, FPGA which are used in industry. We also try to cover the practical questionnaires related to these topics which are asked in the interviews of product/service based semiconductor companies.

Pages

  • Home
  • Synthesis Questionnaries
  • STA Related Questionnaries
  • SoC Concepts
  • DFT
  • FPGA Prototyping
  • CDC Simplified
  • Low Power Concepts
  • Contact Us

Saturday, July 1, 2017

Clock Gating - All You Need to Know


Read more »
at 9:14 PM No comments:
Email ThisBlogThis!Share to XShare to FacebookShare to Pinterest
Labels: clock gating, low-power
Newer Posts Older Posts Home
Subscribe to: Posts (Atom)

Contact Form

Name

Email *

Message *

Search This Blog

Design4Silicon

Design4Silicon
Share and Learn

Like Us on FB

Translate

Live Feed

Labels

hold (3) setup (3) block ram (2) distributed ram (2) synthesis report (2) ASIC flow (1) Backend (1) CLB and LUT (1) Clock Delay (1) Clock Tree Delay (1) D flip flop timing analysis (1) DC (1) DCM (1) DRC and LVS (1) Design constraints (1) Design environments (1) FPGA prototyping (1) FPGA vs ASIC (1) Frontend (1) Glitch (1) Global Buffers (1) Hard and Soft Processor Core (1) Incremental optimization (1) Jitter (1) LBIST and MBIST (1) PLL and DLL (1) RAM HDL coding technique (1) RC (1) RTL2GDSI (1) Skew (1) Synthesis (1) Synthesis flow (1) Uncertainty (1) aocv (1) asic synthesis vs fpga synthesis (1) clock gating (1) combinatorial logic (1) contamination delay (1) depth based ocv (1) distance based ocv (1) early path (1) edif (1) edn (1) emulation platform (1) examples of setup and hold (1) fast to slow (1) hold violation (1) late path (1) low-power (1) mcp (1) metastability (1) modal coverage (1) multicycle (1) netlist simulation (1) ocv (1) on chip variations (1) pre silicon validation (1) precision (1) set_multicycle_path (1) set_timing_derate (1) setup and hold (1) setup and hold time (1) setup violation (1) slow to fast (1) synplify pro (1)

Wikipedia

Search results

Featured Post

OCV and AOCV (Advanced On-Chip Variations)

Total Pageviews

Blog Archive

  • ▼  2017 (4)
    • ▼  July (1)
      • Clock Gating - All You Need to Know
    • ►  March (1)
    • ►  February (1)
    • ►  January (1)
  • ►  2016 (14)
    • ►  September (1)
    • ►  May (1)
    • ►  April (1)
    • ►  March (4)
    • ►  February (4)
    • ►  January (3)

Followers

Search This Blog

Popular Posts

  • Multicycle Path - All You want to Know
  • OCV and AOCV (Advanced On-Chip Variations)
  • FPGA Interview Questions and Answers
  • Synthesis Introduction - A Practical Approach
  • Front End Information - Design to Simulation
  • Basics of Setup and Hold Part -2
  • Back End Information - Synthesis to Bit file Generation
  • Basic of Setup and Hold
  • Basics of Setup and Hold Part - 3
  • High Fanout Synthesis
design4silicon.com. Simple theme. Powered by Blogger.