user constraint file fpga

Sometime we may required or need to control the placing the modules, particular PIN muxing, some timing directives in the FPGA design. We can do it by passing ‘Constraint File’ to the tool along with rtl files. In constraint file we can write following constraint -

• Grouping Constraints

• Logical Constraints

• Physical Constraints

• Mapping Directives

• Placement Constraints

• Routing Directives

• Synthesis Constraints

• Timing Constraints

• Configuration Constraints

Most of tool vendors have their own set of way of writing these constraints. Example Xilinx ISE has with file extension “.ucf” (User Constraint File), Synopsis has different and so on. Here we briefly discuss some important and frequently used design constraints used in Xilinx ISE.

First discuss the elements which frequently used in constraint file i.e. INST, NET and PIN.

1. An INST (instance) - it refers to a primitive instance (like a flip-flop or BRAM or SRL or LUT) or to a hierarchical instance (the instantiation of a module/entity).
2. A PIN (pin on an instance) - either a primitive instance or a hierarchical instance. So the D and Q on a flip-flop are pins. Also when you instantiate a module/entity that has a port (named A), when the module/entity is instantiated, the instance has a PIN named A.
3. A NET is something that connects pins together.

Let’s discuss most important constraint in FPGA Prototyping which is “Timing Constraint”.

Timing specification can be applied to entire device or PIN or NET or INST or to specific group in design. Here some examples

# Define Period

NET  “sys_clk”  TNM_NET  =  “sys_clk” ;

TIMESPEC “TS_sys_clk”  =  PERIOD “sys_clk” 10 ns  HIGH  50% ;

# Related Clock

NET “sys_clk_2”  TNM_NET  =  “sys_clk_2” ;

TIMESPEC “TS_sys_clk_2”  =  PERIOD  “sys_clk_2”  “TS_sys_clk” * 2 ;

# Related Phased Clock

NET “sys_clk_90”  TNM_NET  =  “sys_clk_90” ;

TIMESPEC “TS_sys_clk_90”  =  PERIOD  “sys_clk_90”  “TS_sys_clk”  * 1 PHASE + 2.5ns ;

# Generated Clock

NET  “sys_clk_gen”  TNM_NET  =  “sys_clk_gen” ;

TIMESPEC  “TS_sys_clk_gen”  =  PERIOD  “TS_sys_clk” * 1 ;

# OFFSET

#• The first, global OFFSET applies to all inputs or outputs for a specific clock.

#• The second, a group OFFSET form, identifies a group of inputs or outputs clocked by a common clock that have the same timing requirements.

#• The third, a specific OFFSET form, specifies the timing by each input or output.

# Examples

NET  sig*  OFFSET  =  IN  <value units>  BEFORE <clock_pad_net>  ;

# ‘value unit’ time allowed for data to propagate from pad to meet a setup requirement to clock.

NET  sig*  OFFSET  =  OUT  <value units>  AFTER  <clock_pad_net>  ;

# ‘value unit’ time allowed for data to propagate from synchronous element (clock to out) to pad.

# From PAD to PAD

TIMESPEC “TS_p2p”  =  FROM  “pad”  TO  “pad”  10 ns ;

# When some net or paths are timing independent or mutually exclusive timing then we define those as “FALSE PATH”. It help tool to place those nets or paths which are time critical. Ex.

NET  “net_name”  TIG  ;

INST  “inst_name”  TIG  ;

PIN  “instance.pin_name”  TIG  ;

# FALSE PATH by TIMING PATH

TIMESPEC  “TSid”  =  FROM  “from_grp”  TO  “to_grp”  TIG ;

TIMESPEC  “TSid”  =  FROM  “from_grp”  THRU  “thru_pt”  TO  “to_grp”  TIG ;

# MULTI CYCLE PATH and SLOW FAST EXCEPTIONS

TIMESPEC “TS_sys_clk1_to_sys_clk2”  =  FROM “sys_clk1”  TO  “sys_clk2”  20 ns ;

There are three basic method for creating groups

1. By Connectivity
1. NET  “net_name”   TNM_NET  =  qualifier  “tnm_name” ;
2. By Hierarchy
1. INST “inst_name”  TNM  =  qualifier  “tnm_name” ;
3. By Element

An optional qualifier of FFS, PADS, RAMS, BRAMS_PORTA, BRAMS_PORTB, CPUS,

MULTS, HSIOS or LATCHES may be used.

# Group Elements By Element Output Net Name Schematic User (TIMEGRP)

TIMEGRP  identifier  =  element  (output_netname) ;

• identifier is the name for the new time group.
• element can be FFS, All Pads, Input Pads, Output Pads, Bi-directional Pads, 3-stated Output Pads, RAMs, LATCHES, or User Groups.
• output_netname is the name of the net attached to the element.

Eg.

TIMEGRP  FF_grp  =  FFS (“U1/*”) ;

After ISE now Xilinx has launched new powerful tool for newer FPGA Like Virtex-7 or higher has named Xilinx Vivado and now major industry using this for FPGA Prototyping. It uses XDC file instead of UCF, it has lot more capability than UCF. We can easily change syntax for XDC from UCF.

UCF (User Constraint File)	XDC (Xilinx Design Constraint)
TIMESPEC PERIOD	create_clock
OFFSET IN	set_input_delay
OFFSET OUT	set_output_delay
TIG	set_false_path
FROM/THRU/TO	Set_multicycle_path set_max_delay/set_min_delay
TNM	create_path_group
INST “X” LOC =	set_property LOC

# Define Period

create_clock  -name  sys_clk  -period  10  [get_ports  sys_clk]

# Define Period with HIGH 40% and input Jitter 200ps

create_clock  -name  sys_clk  -period  10  - waveform {0.0 4}  [get_ports  sys_clk]

set_input_jitter  0.2  [get_clocks  sys_clk]

# Generated Clock

create_generated_clock  -name  sys_clk_2  -source  sys_clk  -divide_by  2  sys_clk_2

or

create_generated_clock  -name  sys_clk_2  -source  sys_clk  edges  {1,3,5} sys_clk_2

# OFFSET

# Input Delay

set_input_delay  -max 7  -clock  clock_input  [get_ports  input_data*]

set_input_delay  -min 3  -clock  clock_input  [get_ports  input_data*]

# Output Delay

set_output_delay  -max 4  -clock  clock_input  [get_ports  output_data*]

# False Path

set_false_path  -from  [get_clocks  sys_clk]   -to  [get_clocks  jtag_clk]

set_false_path  -through  [get_pins  MUX/S]

# Asynchronous/Exclusive Clock Groups

set_clock_groups  -physically_exclusive  -group  [get_clocks CLK0]  -group  [get_clocks CLK1]

set_clock_groups  -asynchronous -group [get_clocks CLK0]  -group  [get_clocks CLK1]

# Multicycle Paths - setup and hold

____________   multicycle path = 2T ____________

|      REGA |   -----------------------------> |     REGB |

|Q          D|-----<_Combo_logic_>------|Q           D|

| | | |

| ---|> |     |----|> |

| |__________ |     | |__________|

CLK____|________________________________ |

set_multicycle_path  -from  REGA/CLK  -to  REGB/D  2

set_multicycle_path  -from  REGA/CLK  -to  REGB/D  2  -hold 1

# Physical Constraint

set_property  LOC  H18  [get_nets  RESET]

Complete Soon !!