STA Related Questionnaries

Here i am writing some questions which are totally based on my experience which i have come across during my professional career until now. I would keep appending this as i encounter any new one. I would also like to thank some of my friends from the same domain who have given me some inputs as well. I would also motivate you to share your experience, it can be a single question in any domain. After all "Sharing knowledge is the best way to learn". Hope you appreciate this and share among your friends as well.

Question: What does -start and -end option signifies with set_multicycle_path sdc command.
Answer > Please refer to my article http://www.vlsiconceptsblog.blogspot.com/2016/03/multicycle-path-all-you-know-about.html

Question: How to find maximum operable frequency of a design when max and min delay of a path (net/cell) is given.
Question: How a maximum number of fanout of a CMOS cell is determined?
Answer > The maximum capacitive load of a cell determines the maximum number of fanouts, that is, how many other cells it can drive. And the output drive determines the maximum capacitive load that can be driven. The inverse of pull-up/pull-down resistance is called the output high/low drive of the cell. A higher output drive corresponds to a lower output pull-up and pull-down resistance which allows the cell to charge and discharge a higher load at the output pin.

Question: For slow to fast and fast to slow clock crossings where the setup and hold checks will be performed (at which edges) w.r.t launch clock.
Answer > Please refer to my article http://www.vlsiconceptsblog.blogspot.com/2016/03/multicycle-path-all-you-know-about.html

Question: What is difference between OCV and Advanced-OCV.

Answer > On-Chip variations caused due to variations in PVT condition across the same die or die-to-die. To account for these variations we use concept of OCV and AOCV derating. OCV derating uses fixed derating factors which is constant for cells and nets to account for global chip variations whereas AOCV determines derate values as a function of logic depth and/or cell, and net location. OCV is more pessimistic than AOCV.
Question: In Advanced-OCV why derate decreases with increasing depth?

Question: What are clock gating techniques and why a latch is required, explain with the timing diagram how glitch occurs.

Question: What is difference between set_disable_timing and set_false_path.

Answer > Set_disable_timing is generally useful to disable a particular arcs within the cell. Set_diable_timing and set_false_path both restrict the timing analysis of a particular path but the difference is that with set_false_path still the path delay will be calculated but will not be reported where as set_diable_timing will remove the timing path from analysis.

Question: What is min_pulse_width check and why is this used.

Question: What is difference between GBA and PBA analysis.

Question: What is jitter, its causes and its types.

Answer > Clock jitter is a characteristic which is generally related to clock source generator circuitry and the clock signal environment. Clock jitter is the deviation in the clock waveform (clock edges) w.r.t the ideal waveform. Jitter can be modeled by adding uncertainty regions around the rising and falling edges of a clock. Some basic jitter types include period jitter, cycle to cycle jitter, phase jitter e.t.c. Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a number of randomly selected cycles. Cycle to cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. These types of jitters are used to model different scenarios based on the applications. Some sources of jitter include internal circuitry of PLL, Random thermal noise from a crystal, Resonating devices, transmitters, receivers, connectors etc.

Question: What are virtual clocks? how are are defined and what is the need of virtual clocks.

Answer > Virtual clocks are those clocks which neither exists physically nor logically connected to any ports in the design. They are defined as the normal clock definition without mentioning any source {get_ports}. Basically virtual clocks are used to constrain IO's which are driven through clocks, which doesn't exists in current block.

Question: How timing of other groups will be affected when input/output delay is changed.

Answer > If set_input_delay and set_output_delay is reduced it will improve in2reg and reg2out timing. It will not have any impact on reg2reg timing. Output delay is subtracted from the clock period and you have to meet reg2out path in remaining time. If output delay is less, you get more time to meet reg2out path. Similar thing is applicable for input delay.

Question: What are timing loops? How they are handled and their impact on the timing analysis.

Question: How a clock gating check is inferred? what does a low and high check signifies?

Question: What does check_timing command does?

 Answer > Check_timing command reports the possible timing problems which are in the design. There are some basic timing checks which this command checks before reporting the timing reports which includes multiclock/noclock reaching sequential pins, design has some unmapped cells (generic), clocks which are not propagated, no input delay defined, unconstrained end points etc. Checks performed by this command can be overridden to do some extra checks apart from the default one.

Question: If a timing path is not reported in a primetime what could be the cause or how you will debug that path?

Answer > If a intended timing path is not shown in prime time, this could be due to constraint problem. Either the path is unconstrained (which anyways will be shown in timing shell) or due to some applied exception which is blocking the path from being reported. In such scenario analyze_path command can be used which identifies timing exception and constraints on a particular timing path (cause of blockage).

Question: How would you check for your constraints coverage for a big design?

 Answer > Many designs have numerous and vast set of constraints. In a muti-mode multi-corner design it is very hard to find the constraint coverage, it means whether you have covered your design with full set of constraints or not. report_analysis_coverage command is used to check the coverage of constraints. This command basically check whether your end point (or timing arc) is tested or not. The end point is tested for the following checks setup and hold, min_pulse_width, min_period, clock_gating_check etc. PT generates a detailed report giving the list of tested and untested checks. with this report one can easily debug on the constraint part.

Question:  How setup and hold time of a flop is calculated, which is defined in the .lib files?

Answer  > Refer to the link below http://www.edn.com/design/analog/4371393/Understanding-the-basics-of-setup-and-hold-time

Question: What are different types of timing corners used during signoff STA and why they are required?

Question: What are the different ways of fixing setup and hold violations?

Question: What are the extra timing checks performed apart from setup and hold?

Question: What is AOCV and how the derating is calculated based on the logic depth in AOCV?

Question: Why different corners are required for timing closure and what is difference between RCmax and Cmax timing corner?

Question: If you have both setup and hold violation for a particular end point then how it will be fixed?

Question: What are source synchronous paths and how they are considered as timing critical?

Question: What is CRPR? How it is cancelled in setup and hold checks?

Question: What is recovery and removal checks?

Question: How max_transition violations are fixed?

Answer  max_tran is a highest priority drc check. If the trans is bad (or more) then it will lead to large delays and also will impact the dynamic (switching) power. Usually clock nets should have minimum transition values. Trans violation can be fixed by buffering the net, Up-sizing the driver cell, decreasing the spacing between cells or decreasing the wire length.
Question: Suppose i have a long chain of buffers connected back to back and i have defined clock (using create_clock) on the buffer output then what will happen?
Question: If i have two clocks in the input of 2:1 Mux and select line is unconstrained then is there will be any glitch on the output? If yes then how to remove that glitch