Firstly we will understand what is clock gating and why it is needed, then briefly going through the techniques which are available and the different timing checks which are required for clock-gating.
What is Clock Gating and Its Requirement:
As we are proceeding into lower technology nodes, power is becoming the important factor. Many big companies like Intel, Qcomm, Mediatek e.t.c are facing tough competition to achieve low power dissipation for their chips. Clock gating is one of the technique through which one can reduce the power consumption of a design. The synchronous design style is used by most of the designers now a days. In such synchronous circuits, most of the power is consumed in the clock network. The clock network is responsible for flipping of the flip-flop (FF) (also known as Switching Activity) and processing of the combinational logic. It is the change in FF states that affects power consumption. So with the help of clock gating technique the switching activity of a circuit can be reduced thus reducing the overall dynamic power of a circuit. The clock gating is one of the most vital techniques, which reduces clock network power. By insertion of clock gating cells in a design, dynamic power is reduced.
One can have a look at the following figure, this is the basic implementation of a clock gating circuit. As one can see we have a MUX in front of a register, having one of the inputs coming from the feedback of the register output. The select line of a mux is controlled by a combinational logic. When EN is 0 the same value is latched through the feedback Mux. In this case still the MUX is active and also the register consumes the clock while the value of the register do not change. When EN is 1 new data is fed to the register.
We can eliminate this feedback loop through MUX by inserting a clock
gating circuit as shown below. The clock which is GATED CLK going to
flip flop 2, is being controlled by AND gate which is further dependent
on the Latch EN.
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