FPGA Prototyping

No one wants bugs in silicon when it goes to customer or user, it costs a huge amount of money for respin of all chips and hurts the company's reputation in market. So if we can model a system and test it before silicon, then it will give us more confidence. This idea has introduce the concept of FPGA Prototyping into silicon design flow. So basically it is the process of Modeling RTL design in FPGA such that FPGA can emulate the desired system.

FPGA Prototyping is a new process and users may have various questions in their mind like,

1.    Why do we need it, when IP/SoC verification already exist ?

2.    Where we can use it ?

3.    What are the inputs required for it ?

4.    What is the flow for FPGA Prototyping ?

5.    What are its limitations ?

Actually above are the first few questions that came to my mind when I heard the term 'FPGA Prototyping' for first time, and believe me finding answers for all those type of questions are not difficult, you may need to google it from different sites. In this post I will be trying to answer all the queries which you need to know for FPGA Prototyping.

FPGA is acronym for Field Programmable Gate Array. We can program and use it like any logic circuit. Before knowing about FPGA architecture I assumed it as something having thousands of NAND or NOR gates and I can program it to make any logic circuit. My assumption was wrong in FPGA architectural part but correct in behavioral aspect, that we program it to make any logic circuit.

Coming back to the above questions I will try to answer them in detail, so that we can understand the basic of FPGA Prototyping

• Why do we need FPGA prototyping, when IP/SoC verification already exists ?

First of all we need to understand that FPGA Prototyping is not an alternative for IP/SoC verification. IP/SoC verification has its own importance in Silicon Design Flow. As an example let's take a case where we need to verify an IP like RTC (Real Time Clock). Here we know that to simulate a single minute in Verification take more than an hour, then we can very well understand that it would be a nightmare to attempt to simulate one hour of RTC in verification. The other example is when an IP has large register set, then millions of combinations can exist but it is not possible to cover all combinations in verification and even overnight regression can only cover few hundreds of test cases.

Similarly there are may other cases where regression time plays a critical role and FPGA Prototyping can help to complete testing of all combinations. FPGA system clock is typically in MHz and depends on design size, which makes it much more faster than verification.  

• Where we can use FPGA Prototyping ?

We have seen one example in previous answer where we can use FPGA Prototyping in Validating IP and gain confidence. This process of FPGA Prototyping used in validating IP before silicon arrives is called Pre-Silicon Validation.

Also today SoC's run huge applications and previously software development teams wait till silicon to arrive then start developing software code on it. But by using FPGA Prototyping software team don't need to wait till silicon, now they can complete all driver and application code much before the silicon arrive.

So FPGA Prototyping is very useful in Pre-Silicon Validation as well as Software development well before actual hardware comes.

• What are the inputs required for FPGA Prototyping ?

Only one input required for FPGA Prototyping which is synthesizable RTL design. That means RTL design without all those elements which cannot be synthesized like analog IP's, pads and delay elements etc.

• What is the flow for FPGA Prototyping ?

Similar to ASIC Design flow there is FPGA Design flow. Most of the part of this flow is done by tool only, we need not do any manual work for it which makes it easy to create and use.

               FPGA Prototyping Design Flow

In the above design flow 'Front End' part involves manual work while all 'Back End' part work can be automated by tools.

• What are its limitations ?

FPGA Prototyping has it's advantages and limitations

1.    Design Limitation:  It can work on only synthesizable digital design.

2.    Speed Limitation:  It is thousand time faster than verification but it is generally 10-100 times slower than ASIC.

3.    Debug Limitation:  In verification, user can take complete waveform dump and debug the design, while in FPGA we have some tools available where user can configure a 'Trigger' and take a waveform dump but this can be done only for limited signals due to memory constraint of FPGA.

4.    Coverage Limitation: In FPGA user can calculate functional coverage but other parameter like code coverage cannot be calculated. 

Wait!Wait!Wait!..

This is not the end, from here the wonderful journey begins to wards FPGA Prototyping. You can get useful information at each step of FPGA Prototyping in following link.

·         Front End Information - Design to Simulation.

·         Back End Information - Synthesis to Bit File Generation.

Other important links

• FPGA Interview Questions and Answers

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